1. Field of the Invention
This invention relates to a semiconductor integrated circuit such as a differential amplifier or operation amplifier including a differential source-coupled field effect transistor circuit having a pair of MESFETs (Schottky barrier gate type field effect transistors) or a pair of MOSFETs (insulated gate type field effect transistors).
2. Description of the Related Art
FIG. 1 shows an ordinary differential transistor circuit using a pair of MESFETs and FIG. 2 shows a plane pattern of the circuit. In FIGS. 1 and 2, source electrode S is used commonly for two MESFETs Q1 and Q2. Source electrode S is connected to source electrode wiring LS including source terminal TS. Drain electrodes D1 and D2 are respectively connected to drain electrode wiring LD1 including drain terminal TD1 and drain electrode wiring LD2 including drain terminal TD2. Gate electrodes G1 and G2 are respectively connected to gate electrode wiring LG1 including gate terminal TG1 and gate electrode wiring LG2 including gate terminal TG2. In FIG. 2, reference numerals 11 and 12 respectively denote connecting portions between gate electrodes G1 and G2 of FETs Q1 and Q2 and metal wirings LG1 and LG2. Further, region 10 surrounded by broken lines indicates the position of an active region including L.sup.+ -type source and drain regions of high impurity concentration formed in a semi-insulative GaAs substrate.
In a case where the offset voltage of the differential transistor circuit is reduced, it is important to match the electric characteristics such as transmission admittances or drain voltage-current characteristics of two FETs to each other (hereinafter, matched electric characteristics are referred to as a pair property). For this reason, the shapes and materials of corresponding portions of a pair of MESFETs Q1 and Q2, for example the impurity concentration distributions of the channel active layer and the sizes thereof, are set equal to each other. If the pair property of paired FETs Q1 and Q2 is satisfactory, the same variations will occur in the electrical characteristics of the FETs even when the power source voltage or temperature has changed. As a result, occurrence of the offset voltage can be prevented and stable operation can be attained.
In a circuit having a pattern designed as shown in FIG. 2, since drain electrodes D1 and D2 are disposed extremely close to each other, the pair property of FETs Q1 and Q2 can be set relatively satisfactorily. However, the circuit has a drawback in that the operation speed is low. The drawback is explained below with reference to FIG. 3.
In FIG. 3, the abscissa indicates width WG of each of electrodes G1 and G2 and the ordinate indicates propagation delay time Tpd of a differential transistor circuit including FETs having gate electrode width WG. Propagation delay time Tpd represents time required for an output signal appearing between output terminals TD1 and TD2 to reach a predetermined measured potential (for example, a potential which is 50 % of the amplitude of the signal) after a differential input signal of rectangular pulse wave is applied between input terminals TG1 and TG2. In general, as gate electrode width WG increases, the gate current increases and propagation delay time Tpd tends to decrease as shown by curve A in FIG. 3. Actually, however, as shown by curve B of FIG. 3, propagation delay time Tpd increases when gate electrode width WG becomes larger than a preset value. As a result, the operation speed of the differential transistor circuit having the pattern shown in FIG. 2 cannot be sufficiently enhanced even if gate electrode width WG is increased. The reason why a lower limitation is put on the propagation delay time Tpd is that the input parasitic capacitance of the FET and the voltage drop in distributed equivalent resistor R of the gate electrode increase with an increase in gate electrode width WG.
As described above, with the ordinary differential transistor circuit having the pattern shown in FIG. 2, the relatively satisfactory pair property of the paired FETs can be attained, but the operation speed thereof cannot be sufficiently enhanced.